U.S. patent application Ser. No. 09/466,401, entitled xe2x80x9cbi-directional ESD Diodexe2x80x9d filed concurrently herewith for Roy A. Colclaser and David M. Szmyd, and assigned to the assignee hereof, contains subject matter related to the subject matter of the present patent application.
1. Field of the Invention
The present invention is directed to a device used for protecting circuits against electrostatic discharge (ESD), and more particularly, to an ESD diode having a reduced capacitance.
2. Discussion of the Prior Art
FIG. 1 shows conventional circuit arrangement 100 which is protected against electrostatic discharge (ESD). The device being protected is a circuit 110, which may be formed on a semiconductor substrate of an integrated circuit or chip. The input 115 and output 120 of the circuit 110 are connected to input and output pads 125, 130, respectively, which in turn are connected to pins of the integrated circuit or chip.
Typically, the input 115 and output 120 of the circuit 110, are protected against an electrostatic discharge (ESD) using diodes D1, D2, D3 and D4 connected between the input/output pads 125, 130 and power lines. The power lines include a ground bus 135 and a power supply bus 140, which is connected to a voltage source for providing a positive voltage, referred to as Vcc.
As is well known in the art, each of the diodes D1, D2, D3 and D4 is formed by a P-N junction, and may be integrated on the same chip or integrated circuit that includes the circuit 100 to be protected. For protection against positive ESD, the diodes D1, D2 have their anodes (P-side) connected to the input 115 and output 120 of the circuit 110. The cathodes (N-side) of the diodes D1, D2 are connected to the power supply bus 140 having the positive voltage Vcc. For protection against negative ESD, the diodes D3, D4 have their cathodes (N-side) connected to the input 115 and output 120 of the circuit 110. The anodes (P-side) of the diodes D3, D4 are connected to the ground bus 135. FIG. 1 shows the anode (P-side) of the diode D1 as numeral 145 and the cathode (N-side) as numeral 150. It is understood by those skilled in the art that the discussion of the diode D1 is for illustration purposes, and is equally applicable to all the diodes D1-D4.
As is well known in the art, each diode (e.g., diode D1) blocks current when reverse biased, which is when the cathode (N-side) 150 is made positive with respect to the anode (P-side) 145 until the cathode voltage is high enough to cause breakdown. In the reverse bias mode of operation, the current from the cathode 150 to the anode 145 is very low and is called leakage current.
When the anode 145 or P-side is made positive with respect to the cathode 150 or N-side, the mode of operation is referred to as forward bias. Further, the voltage across the diode D1 is referred to as the forward bias voltage, which is the voltage from the anode 145 to the cathode 150. If the forward bias voltage is increased across the diode D1, the current from the anode 145 to the cathode 150, referred to as the anode current, increases exponentially with the voltage as shown by the plot 410 shown in FIG. 4. For a typical silicon diode, the effect of this rise in current switches the diode D1 into an ON state at a threshold or TURN-ON voltage VT of approximately 0.7 volts. Above this TURN-ON voltage VT, i.e., in the ON state, the voltage increases gradually while the current increases significantly. Note that under high current conditions, e.g. during an ESD event, the voltage across the diode can rise to several volts, due to the internal resistance of the diode.
As shown in the plot 410 of FIG. 4, the diodes D1-D4 provide an open circuit in the reverse direction or block current flow from the cathode 150 to the anode 145. When the voltage on anode 145 is greater than the voltage on the cathode 150 by the TURN-ON voltage VT, the diode D1 turns on in the forward direction, and provides a relatively low resistance path for current flow from the anode 145 or P-side to the cathode 150 or N-side.
ESD events can occur with either polarity between any pair of pins on an integrated circuit. ESD protection must therefore be provided from each input/output pin to both the power supply bus 140 and the ground bus 135 and to all other input/output pins. In addition, ESD protection is required for both positive and negative polarities between the power supply bus 140 and the ground bus 135. For a positive ESD to the input/output pads, e.g., the input pad 125, with respect to the ground bus 135, the ESD current passes through diode D1 to the power supply bus 140. Next, this ESD current passes to the ground bus 135 though a clamp structure 155 which is located between the power supply bus 140 and the ground bus 135. For a negative ESD to the input pad 125 with respect to the ground bus, the ESD current passes through diode D3 to the ground bus 135.
For positive ESD to the input/output pads 125, 130 with respect to the power supply bus 140, the ESD current passes through diodes D1, D2 to the power supply bus 140. For a negative ESD to the input/output pads 125, 130 with respect to the power supply bus 140, which is the same as a positive ESD from the power supply bus 140 with respect to the input/output pads 125, 130, the ESD current passes through the clamp structure 155 and through the diodes D3, D4 to the pad.
For a positive ESD between input/output pads 125 and 130, the ESD current passes through diode D1 to the power supply bus 140, through the power supply clamp 155 to the ground bus 135 and through the diode D4. For a negative ESD between input/output pads 125 and 130, the ESD current passes through diode D2 to the power supply bus 140, through the power supply clamp 155 to the ground bus 135 and through the diode D3.
For positive ESD between the power supply bus 140 and the ground bus 135, the ESD current passes through the power supply clamp 155. For negative ESD between the power supply bus 140 and the ground bus 135, the ESD current passes through one or more of the series diode strings D1 and D3 or D2 and D4.
The conventional ESD protected circuit arrangement 100 provides an effective protection scheme for many situations. However, when reverse biased, each diode D1, D2, D3 and D4 provides a capacitive load on input/output signals which can significantly degrade the input and output signals and performance of the circuit 110, particularly at high frequencies. Thus, the major disadvantage of the conventional diode D1 occurs during normal (non-ESD) operation. In this case, the diodes D1, D2 connected between the input or output pins or pads 125, 135 and the power supply line 140, as well as the diodes D3, D4 connected between ground 135 and the pads 125, 135, are reverse biased where an analogue input signal is biased between the power supply and ground.
Each of the diodes D1-D4 has a capacitance that is associated with the diode P-N junction where the capacitance depends on the area and the doping configuration. Part of the high frequency input signal is diverted through the diodes to circuitry other than the intended path. Reducing the size or area of the diodes reduces the capacitance, but it also reduces the level of ESD protection, since the level of ESD protection depends on the current density in the diode.
Accordingly, there is a need to reduce capacitive loads connected to input/output lines while maintaining a desired level of ESD protection.
The object of the present invention is to provide an electrostatic discharge (ESD) protection device that significantly reduces the problems of conventional ESD protection devices.
The present invention accomplishes the above and other objects by providing an ESD protection device, referred to as an ESD diode for example, which protects a circuit against electrostatic discharge and allows proper operation, particularly at high frequencies. The ESD diode has four adjacent regions. The first and third regions are formed from a semiconductor substrate having a P-type conductivity. The second and fourth regions are formed from the semiconductor substrate having an N-type conductivity. The first region is for connection to a signal terminal of the circuit being protected when the fourth region is connected to a positive power line of the circuit. The fourth region is for connection to the signal terminal when the first region is connected to the ground line or a negative power line of the circuit.